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Design of Digital Circuits SS11

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- 4.5.2012 Joel Reardon presents the paper "User-level Secure Deletion on Log-structured File Systems" at ASIACCS in Seoul, Korea.
- 16.4.2012 Aanjhan Ranganathan presents the paper "Physical-Layer Attacks on Chirp-based Ranging Systems" at WiSec in Tucson, Arizona.
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252-0014-00L (6 ECTS)
Lectures: Fri 13:15-16:00, HG F 3

Exercises: CAB H56, H57 3 time slots according to groups :
Mon 10:15-12:00
Wed 13:15-15:0
Fri 8:15-10:00

People:

Course responsible:
Prof. Dr. Srdjan Capkun, ETHZ <capkuns@inf.ethz.ch>
Dr. Frank K. Gurkaynak <kgf@ee.ethz.ch>

Teaching assistants:
Dr. Aurélien Francillon <aurelien.francillon@inf.ethz.ch>
Aanjhan Ranganathan <raanjhan@inf.ethz.ch>
Changil Kim <kimc@disneyresearch.com>

Student teaching assistants:
Luka Malisa <malisal@student.ethz.ch>
Adarsh Amirtham <adarsha@student.ethz.ch>
François Serre <serref@student.ethz.ch>
Gürel Ugur <uguerel@student.ethz.ch>
Sencer Akcan <akcans@student.ethz.ch>

Schedule:

Lectures (13 weeks): 25.02.2011; 04.03.; 11.03.; 18.03.; 25.03.; 01.04.; 08.04.; 15.04.; 06.05.; 13.05.; 20.05.; 27.05.; 03.06.

Exercises (12 weeks): First two exercise sessions (25.02. 04.03.) replaced by homework assignments.
There are three slots for exercises/lab :
Monday 10:15-12:00 or Wednesday 13:15-15:00 or Friday 8:15-10:00

Exercises Monday 07.03.; 14.03.; 21.03.; 28.03.; 04.04.; 18.04.; 02.05.; 09.05.; 16.05.; 23.05.
Exercises Wednesday 09.03.; 16.03.; 23.03.; 30.03.; 06.04.; 13.04.; 04.05.; 11.05.; 18.05.; 25.05.
Exercises Friday 11.03.; 18.03.; 25.03.; 01.04.; 08.04.; 15.04.; 06.05.; 13.05.; 20.05.; 27.05.

Content:

About the course:
The course provides an introduction to the design of digital circuits and computer architecture. The course covers the basics of the technical foundations of gates, an introduction to hardware description languages (and their use in the design process), and introduces processor and computer architecture.

Course content:
- Basic Gates
- Combinational Logic Design
- Sequential Logic Design
- Hardware Description Languages
- Digital Building Blocks
- Computer Architecture
- Microarchitecture

Literature:
The course closely follows the following textbook: Digital Design and Computer Architecture (David Harris and Sarah Harris), Language: English, ISBN-10: 0123704979. This book is available online (within ETH and from home using an ETH VPN connection). The course will (roughly) cover the first 7 chapters of the book.

Evaluation / requirements:

Evaluation:
Written exam (90 minutes). It will be scheduled in the exam period (sessionsprüfung). In the case that you cannot make it to the exam for any reason, please contact the pruefungsplanstelle (+41 44 632 20 68).

Exercises:
- The students are required to hand in 75% of the exercises to access the exam. The exam will include questions related to the exercises.

Schedule (Follow the links for lecture slides, exercise instructions and solutions):

Theoretical exercises are given at the end of the lecture (and in the table below in column "Assignment") and need to be handed-in at the beginning of the following lecture. Solutions to the theoretical exercises (TS) are posted one week after the exercise is given. Practical exercises (Lab) need to be submitted to the assistants during the exercise sessions and according to the schedule.

TS: X.Y refers to the exercise X.Y in the course book (Digital Design and Computer Architecture). Reading X.Y refers to the chapter X.Y of the course book. For the instructions on the practical exercises follow the links below.

To access the content use your ETHZ credentials.

For the Lab exercises it is possible to use :

Lab groups : DD2011_Students_Groups.pdf

No Date Topic Assignment Hand In Reading
1 25-Feb Introduction: digital abstraction; binary
numbers; bits, bytes, and nibbles; logic gates, logic levels,
transistors, power consumption pdf
TS1: 1.19, 1.20, 1.38, 1.39, 1.47 Solutions
Ch. 1, A.1-A.2, A.5-A.7
2 4-Mar Boolean Equations, Boolean Algebra, From
Logic to Gates, Multilevel Combinational Logic, X’s and Z’s, pdf
TS2: 1.49 1.63 2.1 2.7 2.8 2.15 2.17

Solutions

TS1 2.1-2.6
3 11-Mar Karnaugh Maps, Verilog (Combinational) pdf
TS3:2.19 2.20 2.22 2.28 2.32, Solutions

Lab1

TS2 2.7-2.10, 4.1-4.5
4 18-Mar Latches, Flip-Flops, Sequential Logic
Design, FSM, Timing of Sequential Logic pdf
TS4:3.8-3.15, 3.17-3.21, Solutions

Lab2

TS3
Lab1
Ch. 3
5 25-Mar Verilog (FSM) pdf TS5:4.31, 4.38, 4.40, 4.48, Solutions
Lab3
TS4, Lab2 4.6-4.9
6 1-Apr Arithmetic Circuits, ALU, Rotator, Multiplier pdf TS6: 5.2, 5.12, 5.20, 5.23, 5.24, 5.25, 5.26, Solutions
Lab4
TS5,
Lab3
5.1-5.6
(+ TBA)
7 8-Apr Computer Architecture – MIPS pdf TS7: 5.45 5.47 6.7 6.10 6.12, Solutions

Lab5a

TS6,
Lab4
Ch. 6
8 15-Apr Computer Architecture – MIPS pdf TS8: 6.17 6.22 6.24 6.27 6.30, Solutions

Lab5b, Lab files

TS7
Lab5a
Ch. 6
9 6-May Micro-architecture: Single and Multicycle processors pdf TS9,
Lab6, Lab files
TS8, Lab5b 7.1-7.5
10 13-May Advanced and Modern Processors (continuing with slides from lecture 9) TS10,
Lab7a, Lab files
TS9,

Lab6

7.6-7.10
(+ TBA)
11 20-May Memory Systems pdf TS11,
Lab7b, Lap 7b helper files
TS10,
Lab7a
Ch. 8
12 27-May Real world Subsystems TS12,
Lab7c, Lab7c.zip
TS11,
Lab7b
8.5

(+ TBA)

13 3-Jun Example problems, preparation for the
exam
TS12,

Lab7c

7.1, 7.2
14 13-Jun Solution to Exercises - All chapters PDF      
 

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