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Design of Digital Circuits SS13 (6 ECTS)

News / Recent Events

- 2.4.2013: Elli Androulaki presents the paper "Evaluating User Privacy in Bitcoin" at the Financial Cryptography and Data Security Conference in Okinawa, Japan.
- 5.12.2012: Claudio Marforio and Ramya Jayaram Masti present the papers "Analysis of the Communication between Colluding Applications on Modern Smartphones" and "Enabling Trusted Scheduling in Embedded Systems" at ACSAC in Orlando, Florida.
- 18.10.2012 Elli Androulaki presents the paper "Double-Spending Fast Payments in Bitcoin" at ACM CCS in Raleigh, North Carolina.
- 11.9.2012 Aanjhan Ranganathan presents the paper "Design and Implementation of a Terrorist Fraud Resilient Distance Bounding System" at ESORICS in Pisa, Italy.
- 9.8.2012 Joel Reardon presents the paper "Data Node Encrypted File System: Efficient Secure Deletion for Flash Memory" at the USENIX Security Symposium in Bellevue, Washington.

All News / Events

All Media Coverage

 

Lecturers

Markus Püschel, Computer Science, ETHZ <pueschel@inf.ethz.ch>
Frank K. Gurkaynak, Information Technology and Electrical Engineering, ETHZ <kgf@ee.ethz.ch>

Teaching Assistant

Aanjhan Ranganathan, Computer Science, ETHZ <raanjhan@inf.ethz.ch>

Help

For technical questions, please go to the office hours (below) or write to <digitaltechnik@lists.inf.ethz.ch>. All lecturers and assistants will receive this e-mail and try to respond quickly. For other inquiries please email the TA or the lecturers.

Lecture Times

Day Time Room
Tuesday
0815 to 1000 hrs HG E 7
Friday 0915 to 1000 hrs HG G 5

Note: No lectures on 10th of May and 31st of May.

Lab Sessions

Day Time Room Assistants Office Hours (Location) Student Groups
Monday 1015-1200 hrs HG E 26.1
HG E 26.3
Tobias, Claudio, Victoria, Marcela Tuesday 1215-1300 (RZ H7) PDF
Wednesday 1315-1500 hrs
HG E 26.1
HG E 26.3
Francois, Samuel, Cyril, Nicolas Thursday 1215-1300 (RZ H5) PDF
Thursday 1515-1700 hrs HG E 26.1
HG E 26.3
Arthur, Nikolaos, Der-Yeuan, Aanjhan Friday 1215-1300 (CNB F 100.9) PDF

List of students who keep their old lab grades: PDF

In the labs...

Lab Assistants:

Name Email ID
Aanjhan Ranganathan <raanjhan@inf.ethz.ch>
Marcela Zuluaga <marcela.zuluaga@inf.ethz.ch>
François Serre <serref@student.ethz.ch>
Der-Yeuan <dyu@student.ethz.ch>
Arthur Gervais <arthur.gervais@inf.ethz.ch>
Nikolaos Karapanos <knikos@inf.ethz.ch>
Victoria Caparros Cabezas <caparrov@inf.ethz.ch>
Samuel Bryner <brynersa@student.ethz.ch>
Claudio Foellmi <foellmic@student.ethz.ch>
Cyril Steimer <csteimer@student.ethz.ch>
Nicolas Kick <kickn@student.ethz.ch>
Tobias Kaiser <kaisert@student.ethz.ch>

Grading Policy

Written exam: 75 percent
Laboratory exercises: 25 percent

Course Content and Schedule

The course provides an introduction to the design of digital circuits and computer architecture. The course covers the basics of the technical foundations of gates, an introduction to hardware description languages (and their use in the design process), and introduces processor and computer architecture. The lectures closely follow the textbook: Digital Design and Computer Architecture (David Harris and Sarah Harris), Language: English, ISBN-10: 0123704979. This book is available online (within ETH and from home using an ETH VPN connection). The course will (roughly) cover the first 7 chapters of the book.

Lecture Schedule

Week Dates Description Book Chapters Lab
1 19.02
22.02
Organization and Introduction [PDF] , BinaryNumbers [PDF]
EE perspective [PDF]
1.1-1.4
1.5-1.8
 
2 25.02
01.03
EE perspective (contd), Combinational Circuits theory [PDF]
Combinational Circuits theory (contd)
1.5-1.8,2.0-2.3
2.0-2.3
 
3 05.03
08.03
Combinational Circuits Design [PDF]
Combinational Circuits Design (contd), FPGA Systems, Experimental Board [PDF]
2.4-2.9
5.6
Lab 1
4 12.03
15.03
Verilog Combinational Circuits [PDF], Sequential Circuits Design [PDF]
Sequential Circuits Design (contd)
4.2-4.3
3.1-3.4
Lab 2
5 19.03
22.03
Verilog Sequential Circuits [PDF]
Sequential Circuits Timing [PDF]
4.4-4.7
3.5
Lab 3
6 26.03
29.03
Arithmetic Circuits [PDF]
No Lecture
5.2 Lab 4
7 02.04
05.04
No Lecture
No Lecture
  No Lab
8 09.04
12.04
Number Systems [PDF], Advance Adders [PDF]
Verilog Testbenches [PDF]
5.3, 5.2 (extra)
4.8
Lab 5a
9 16.04
19.04
MIPS Assembly [PDF]
Memory Systems [PDF]
6.1-6.3
5.5
Lab 5b
10 23.04
25.04
Single Cycle Architecture [PDF]
Single Cycle Architecture (contd)
7.1-7.3 Lab 6
11 30.04
03.05
MIPS Programming [PDF]
MIPS Programming (contd)
6.4-6.7 Lab 7a
12 07.05
10.05
Cache Systems [PDF], I/O Systems [PDF]
No Lecture
8.2-8.4
8.5
Lab 7b
13 14.05
17.05
Multicycle Architectures [PDF]
Floating Point Numbers [PDF]
7.4 Lab 7c
14 21.05
24.05
Pipelined Architectures [PDF]
Advanced Processors [PDF]
7.5
7.8
 
15 28.05
31.05
Review of the lecture [PDF]
No Lecture
ALL  

Lab Exercises

# Exercise Lab dates Report hand-in
1 Schematic Entry in Xilinx ISE [PDF] Mon 04.03
Wed 06.03
Thu 07.03
Mon 11.03
Wed 13.03
Thu 14.03
2 Mapping a circuit onto the FPGA board [PDF] Mon 11.03
Wed 13.03
Thu 14.03
Mon 18.03
Wed 20.03
Thu 21.03
3 Verilog for Combinatorial Circuits [PDF] Mon 18.03
Wed 20.03
Thu 21.03
Mon 25.03
Wed 27.03
Thu 28.03
4 Finite State Machines [PDF] Mon 25.03
Wed 27.03
Thu 28.03
Mon 08.04
Wed 10.04
Thu 11.04
5a Implementing an ALU [PDF] Mon 08.04
Wed 10.04
Thu 11.04
Mon 15.04
Wed 17.04
Thu 18.04
5b Testing the ALU [PDF][ZIP] Mon 15.04
Wed 17.04
Thu 18.04
Mon 22.04
Wed 24.04
Thu 25.04
6 Writing Assembly Code [PDF][ZIP] Mon 22.04
Wed 24.04
Thu 25.04
Mon 29.04
Wed 08.05 *
Thu 02.05
7a Build the MIPS Processor[PDF][ZIP] Mon 29.04
Wed 08.05 *
Thu 02.05
Mon 06.05
Wed 15.05
Thu 16.05*
7b The Performance of MIPS [PDF][Helper files] Mon 06.05
Wed 15.05
Thu 16.05*
Mon 13.05
Wed 22.05
Thu 23.05
7c Interfacing with the Processor [PDF][ZIP][Helper files]
Mon 13.05
Wed 22.05
Thu 23.05
Mon 27.05
Wed 29.05
Thu 30.05

* Irregular dates due to holidays.

Xilinx Software Installation

The computers in rooms HG E26.1 and 26.3 are already installed with the necessary software. Students who wish to install and experiment on their own can follow the below instructions.

  1. Download XIlinx ISE Webpack from here. In the labs we use Xilinx version 13.4 and recommend the same. Depending on your operating system, select the Full Installer files (approximately 6 GB).
  2. You will have to create a Xilinx account to continue downloading.
  3. After downloading, open the compressed (.tar) file and run “xsetup.exe”.
  4. Follow the instructions for installing Xilinx WebPACK as prompted by the setup wizard.
  5. You will be prompted to finish license configuration, select “Start ISE WebPack”, and click “Next”, and follow the link to finish the registration.
 

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© 2013 ETH Zurich | Imprint | Disclaimer | 27 May 2013
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