Design of Digital Circuits SS17
Spring semester 2017
Course number: 252-0028-00L (7 ECTS)
Thursday, 13:15-15:00, in HG E 7
Friday, 13:15-15:00, in HG E 7
Tuesday, 15:15-17:00 (in HG E 19, E 26.1, E 26.3)
Wednesday, 15:15-17:00 (in HG E 26.1, E 26.3)
Friday, 08:15-10:00 (in HG E 26.1, E 26.3)
Friday, 10:15-12:00 (in HG E 27 and E 26.3)
Prof. Dr. Onur Mutlu, D-INFK ()
Prof. Dr. Srdjan Capkun, D-INFK ()
Victoria Caparros Cabezas, Aritra Dhar, Marco Guarnieri, Hasan Hassan, Jeremie Kim, Sinisa Matetic, Minesh Patel, Francois Serre, Mridula Singh, David Sommer, Arash Tavakkol, Der-Yeuan Yu
Chris Mnuk, Daniel Gstöhl, Kick Nicolas, Artur Gigon Almada e Melo, Josua Cantieni, Andreas Brombach, Carsten Lau Nielsen, Anton Middelhaufe, Erand Smakaj, Alexander Breuss
Grading Policy: written exam: 75 percent, lab exercises: 25 percent
16.04: Lab 7, Week 8,9 online
11.04: Lab 6 online
06.04: Lab 5 and Week 7 contents updated
31.03: Week 6 contents updated
27.03: Lab 4 and Week 5 contents online
20.03: Lab 3 online
17.03: Week 4 contents updated
12.03: Week 3 slides and Lab 2 online
06.03: Lab 1 online
05.03: Week 2 slides online
01.03: Lab time and group assignments are here.
24.02: Lecture videos can be found here.
23.02: Slides for Week 1 uploaded. Digital version of additional reference book will be provided later. Please access it through the department library for now.
22.02: We've created an FAQ for you in the Help section.
22.02: The labs begin in the second week of March.
31.01: Webpage online
This course provides an introduction to the design of digital circuits and computer architecture. It covers the technical foundations of logic gates, an introduction to hardware description languages (and their use in the design process), as well as processor and computer architectures.
Introduction and Basics [ppt (PPT, 20.1 MB)|pdf (PDF, 8.5 MB)]
Mysteries Continued [ppt (PPT, 25.8 MB)|pdf (PDF, 3.9 MB)]
Video: Thursday, Friday
Binary Numbers [pptx (PPTX, 747 KB)|pdf (PDF, 1.2 MB)]
Harris & Harris, Chapter 1
Patt and Patel, Chapters 1 & 2
Introduction to FPGAs (by Der-Yeuan Yu) [pptx (PPTX, 1.3 MB)|pdf (PDF, 774 KB)]
Combinational Circuits (Guest lecture by Frank Gürkaynak) [pptx (PPTX, 3.2 MB)|pdf (PDF, 2.3 MB)]
Combinational Circuits continued from Week 2 (Guest lecture by Aanjhan Ranganathan)
Sequential Circuits (Guest lecture by Frank Gürkaynak) [pptx (PPTX, 1.5 MB)|pdf (PDF, 719 KB)]
Harris & Harris, Chapters 2, 3, 4
Sequential Circuits continuted from Week 3 (Guest lecture by Aanjhan Ranganathan)
Timing and Verification (Guest lecture by Frank Gürkaynak) [pptx (PPTX, 4.5 MB)|pdf (PDF, 1.8 MB)]
MIPS Assembly (Guest lecture by Aanjhan Ranganathan) [pptx (PPTX, 1.5 MB)|pdf (PDF, 1 MB)]
MIPS Programming (Lecture by Der-Yeuan Yu) [pptx (PPTX, 679 KB)|pdf (PDF, 1.1 MB)]
Video: Thursday, Friday
Multi-Cycle Microarch. [ppt (PPT, 6 MB)|pdf (PDF, 5.3 MB)]
Microprogramming [ppt (PPT, 4.7 MB)|pdf (PDF, 3.2 MB)]
Video: Thursday, Friday
Patt and Patel, Chapters 4, 5, Revised Apendix C
The LC-3b ISA [pdf (PDF, 151 KB)]
The Microarchitecture of the LC-3b, Basic Machine [pdf (PDF, 95 KB)]
LC-3b Figures [pdf (PDF, 333 KB)]
Harris & Harris, Chapter 7.4
Optional: Maurice Wilkes, "The Best Way to Design an Automatic Calculating Machine" [pdf (PDF, 297 KB)]
Week 9 (Easter holidays):
Harris & Harris, Chapter 7.6-7.9
Optional: Smith and Sohi, "Microarchitecture of Superscalar Processors", Proc. IEEE, 1995.
- You will work in groups of two. There are 9 labs in total.
- You will do hands-on exercises and be required to demonstrate your implementation.
- The required demonstration is mentioned in the lab exercises sheet at the end of the manual. Only the demonstration is requried, you do not need to hand in the sheet.
Lab 1: Drawing a Basic Circuit [Manual (PDF, 228 KB)]
Lab dates: Tue 07.03, Wed 08.03, Fri 10.03
Lab 2: Mapping Your Circuit to FPGA [Manual (PDF, 830 KB)]
Lab dates: Tue 14.03, Wed 15.03, Fri 17.03
Lab 3: Verilog for Combinatorial Circuits [Manual (PDF, 450 KB)]
Lab dates: Tue 21.03, Wed 22.03, Fri 24.03
Lab 4: Finite State Machines [Manual (PDF, 377 KB)]
Lab dates: Tue 28.03, Wed 29.03, Fri 31.03
Lab 5: Implementing an ALU [Manual (PDF, 386 KB)]
Lab dates: Tue 04.04, Wed 05.04, Fri 07.04
Working with the FPGA Board
For this course, we use the software Vivado for FPGA programming. The computers in rooms HG E26.1 and 26.3 are already installed with the necessary software. If you wish to use your own computer, you can refer to the following instructions:
You can also find examples for the Basys 3 board and a master constraint file here:
For technical questions, please write to . All lecturers and assistants will receive this e-mail and try to respond quickly. For other inquiries please email the TA or the lecturers.
Frequently Ased Questions:
Q: Can I use my lab grades from previous years?
A: Yes. You can look up your past grades here: https://moodle-app2.let.ethz.ch/course/view.php?id=2979
Q: Can I use my lab grades from previous years and still do the labs?
A: Sure! We will provide you with this option in the sign-up form.
Q: Can I do the labs and decide at the end of the semester whether to use the my grades from previous years?
A: No. You need to decide at the beginning of the semester.
Q: I don't have a partner. What do I do?
A: Make new friends and find one:) Otherwise we will assign you with another person who has not found a partner.
Q: Can we have groups of three students?
A: No. We will assign you with another prson who has not found a partner. Groups of two are much better for your learning experience instead of three so we will only make exceptions if absolutely necessary.